1. Field of the Invention
This invention relates to multithreaded processors and, more specifically, to management of virtual and/or real address to physical address translations requests.
2. Description of the Related Art
Modern computer processors typically achieve high throughput through multithreaded cores that simultaneously execute multiple threads. Each thread may include a set of instructions that execute independently of instructions from another thread. For example, an individual software process, such as an application, may consist of one or more threads that may be scheduled for parallel execution by an operating system. Threading can be an efficient way to improve processor throughput without increasing die size. This is particularly true with modern web-oriented and business applications, which typically do not fully utilize the resources of an individual processor pipeline. Multithreading may lead to more efficient use of processor resources and improved processor performance, as resources are less likely to sit idle with the threads operating in different stages of execution.
Current multithreaded processors typically sacrifice single thread performance to achieve an overall, high throughput within the processor. In other words, the aggregate throughput of each core on the processor may be high, but the performance of a single thread on the core may be relatively low. The resources within typical multithreaded processors, particularly resources for handling virtual and/or real address to physical address translations, are designed to support serial instruction execution without any speculative execution along predicted branch paths. For example, memory management resources designed to provide address translation requests that cannot be located in translation lookaside buffers (TLBs) are typically designed to support one address translation request at a time, serially, and to support address translation requests originating only from threads operating on confirmed branch paths.